The present invention relates to a thin film transistor (TFT), and more particularly to a method of forming a TFT by utilizing a highly anisotropic etching process. The present invention also relates to a TFT formed by the inventive method as well as a display device including the inventive TFT.
Thin film transistors (TFTs) have been used in a wide range of semiconductor devices, such as an active matrix type liquid crystal display, an organic electro-luminescence display, and an image sensor. The reason for this is that TFTs typically provide a thin, light weight device that operates with low power consumption.
Although various thin film transistor structures for improving desired properties have been proposed so far, a thin film transistor that has a polymer film on array (PFA) structure typically improves the aperture ratio of a display device. The reason for the improved aperture ratio is that the pixel electrode made of ITO (indium tin oxide) is overlapped over a data line. In such a configuration, an electric field is not applied to a liquid crystal molecule on the ITO electrode so that the region in which disclination lines are created is limited within the region of the data line.
FIGS. 1(a)-(f) shows conventional process steps for forming the above described thin film transistor including the PFA structure. As shown in FIG. 1(a), gate electrode 2 is patterned on insulating substrate 1, which may include glass, by a suitable patterning process (1st photo engraving process; PEP). This prior art process next proceeds to the step shown in FIG. 1(b) wherein gate insulating layer 3 and semiconductor layer 4 are deposited on substrate 1 and gate electrode 2. Next, channel protection layer 5 is deposited and patterned by a suitable patterning process providing the structure shown, for example, in FIG. 1(b) (2nd PEP).
The prior art process further proceeds to a third PEP step wherein source electrode 6 and drain electrode 7 are first deposited and thereafter patterned; See FIG. 1(c). The source/drain electrodes are comprised of the same or different electrode material which is selected from the group consisting of Al, Mo, Ta, W and other like conductive metals.
Passivation layer 8 is next deposited and patterned by a fourth PEP (See FIG. 1(d)), and thereafter interlayer insulator 9 is applied on the previously patterned structure and then interlayer insulator 9 is etched to form openings 10 for contact holes as shown in FIG. 1(e) (fifth PEP). Following the fifth PEP step, an ITO layer is deposited and patterned to form pixel electrode 11 and contact holes 12 through a patterning process as shown in FIG. 1(f) (sixth PEP).
Although the above described process may form a thin film transistor (including a PFA) comprising a pixel electrode (i.e., element 11) having an improved aperture ratio, an extra patterning process, which forms the structure for contact holes 12 through the PFA, is added to the overall process, thereby significantly increasing the production cost of the TFT.
Japanese Patent Publication (Laid-Open) Heisei No.10-170951 discloses a method for forming a liquid crystal display (LCD) device that includes a step of forming contact holes in an inorganic insulating layer so that the contact holes have improved self-alignment properties. The self-alignment of the contact holes is improved by etching the inorganic insulating layer using the interlayer insulator as a resist layer. During this etching step, exposed edges of the inorganic insulating layer are often over etched and the edge of the inorganic insulating layer is recessed under the bottom edge of the interlayer insulator. This gap frequently results in point defects in the display because the pixel electrode is not electrically connected to the TFT or storage capacitor since the thin ITO layer can not bridge the gap. FIG. 2 shows a prior art display device which includes the overhang or gap therein. A gap, or overhang, is shown both at the interface of the interlayer insulator (9) and the inorganic insulating layer (8), see 13, and at the interface of the inorganic insulating layer (8) and the conductor layer which forms the drain electrode (7), see 14. To improve the continuity of the pixel electrode, the interlayer insulator is typically post-baked to obtain a smooth and continuous face between the interlayer insulator and the passivation layer. This process adds another processing step to the overall process flow which, in turn, results in a further increase in the production cost of the thin film transistor.
Japanese Patent Publication (Laid-Open) Heisei No. 10-283934 discloses a process for forming a thin film transistor. The thin film transistor disclosed in this reference is constructed by forming openings for contact holes in an interlayer insulator and then etching a passivation layer to form self-aligned edges of a contact hole in the passivation layer. Although resistance through the contact holes and pixel electrode becomes low, a gap between the interlayer insulating layer and the passivation layer exists such that defects due to the gap might be created. In addition, the disclosed process has less selectivity such that the electrodes, i.e., drain electrode, may be etched out entirely during the etching process when a display device having a large size substrate is formed.
The above conventional thin film transistors and processes for forming thereof are known in the art, the inventors have sought a novel structure which serves to reduce defects caused by the gap between the interlayer insulator and the passivation layer. The reduction in defects caused by the gap between the interlayer dielectric and passivation layer obtained in the present invention improves the performance of a display device including a TFT array while making it possible to provide a large size display device.
The present invention is directed to a novel anisotropic etching process which forms a contact hole having a smooth and continuous inner wall, thereby ensuring electrical contact between the drain electrode and the pixel electrode while reducing the number of processing steps employed in fabricating the TFT. In addition, the present invention provides a thin film transistor as well as a large sized display device that contains the inventive TFT.
Therefore, one object of the present invention is to provide a thin film transistor (TFT) having a high aperture ratio and improved reliability of electrode connection.
Another object of the present invention is to provide a thin film transistor which is capable of being used in a large area display device.
A further object of the present invention is to provide a process for forming a thin film transistor in which reliability of the electrode connection is improved.
A yet further object of the present invention is to provide a process for forming a thin film transistor which includes a reduced number of patterning steps.
An additional object of the present invention is to provide a display device including the thin film transistor of the present invention.
According to a first aspect of the present invention, a thin film transistor formed on a substrate is provided. The inventive thin film transistor comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes containing an ohmic contact layer, wherein said gate insulating layer is formed on said gate electrode and said semiconductor layer is formed on said gate insulating layer; a passivation layer having first openings for contact holes formed on said transistor element; and an interlayer insulator having second openings for the contact holes extending over said passivation layer, said first and second openings are self-aligned with each other over the substrate, and wherein an electrical conductive layer is deposited on an inner wall of the contact hole, said inner wall is formed by the first and second openings tapered smoothly and continuously by an anisotropic etching process.
Note that the above embodiment covers bottom-gate type thin film transistors. Additionally, the present invention also contemplates top-gate type thin film transistors. Specifically, the top-gate type thin film transistor comprises:
a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes, wherein said gate insulating layer is formed on said semiconductor layer and said gate electrode is formed on said gate insulating layer;
a passivation layer having first openings for contact holes formed on said transistor element; and
an interlayer insulator having second openings for the contact holes extending over said passivation layer, said first and second openings are self-aligned with each other over the substrate, and wherein an electrical conductive layer is deposited on an inner wall of the contact hole, said inner wall is formed by the first and second openings tapered smoothly and continuously by an anisotropic etching process.
According to a second aspect of the present invention, a process for forming the inventive thin film transistor on a substrate is provided. The inventive process employed in fabricating the inventive TFT comprises the steps of:
(a) providing a transistor element on a substrate that is capable of supporting a thin film transistor, said transistor element including at least a gate electrode, a gate insulating layer, a semiconductor layer and source and drain electrodes;
(b) depositing a passivation layer to cover the transistor element;
(c) forming an interlayer insulator on the passivation layer and patterning said interlayer insulator to form first openings for contact holes;
(d) patterning the passivation layer by an anisotropic etching process so as to form second openings, said anisotropic etching process having an etch selectivity for the passivation layer to drain electrode that is greater than or equal to 5:1 using an etchant gas comprising fluorine without oxygen (O);
(e) removing etching residues formed by step (d) by a dry etching process including an oxygen (O2) gas; and
(f) forming a pixel electrode and a contact electrode by depositing and patterning an electrical conductive layer, wherein the electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously.
According to a third aspect of the present invention, a display device (including arrayed TFTs on a substrate) having an improved aperture ratio of the pixel electrode is provided. The thin film transistor comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes containing an ohmic contact layer; a passivation layer having first openings for contact holes formed on said transistor element; and an interlayer insulator having second openings for the contact holes extending over said passivation layer, said first and second openings are self-aligned with each other over the substrate, and wherein an electrical conductive layer is deposited on an inner wall of the contact hole, said inner wall is formed by the first and second openings tapered smoothly and continuously by an anisotropic etching process.
Note that in this aspect of the present invention, the thin film transistor may be either a bottom-gate type TFT or a top-gate type TFT.